Moore and Mealy Type synchronous state machine
In this task, a synchronous state machine is considered clocked on the leading edge (the upward flank) of
clock signal φ. The state machine has an input in as well as an output x.
The mode machine’s operation can be described by the output x assuming the value “1”, when and only when
input i has assumed the value “1” in just one of the last two clock cycles
a) Write down a state diagram for a Moore type synchronous state machine, discuss whether the state machine contains equivalent (superfluous) states, and specify which states can
b) Write a state diagram for a Mealy-type synchronous state machine
c) For timing, indicate the behavior of the state machines when the inputs are applied “00011100101”.
Hope someone can help 🙂